This invention relates to servo pulse detection and position error signal demodulation for information storage/retrieval devices, such as magnetic disk drives.
Servo detection and demodulation are commonly used in disk/tape drives in which information is stored on multiple tracks on a storage medium. In order to increase the storage density of these devices, the tracks are placed closer together, resulting in a tighter tolerance specification for positioning the read/write head over the surface of the medium. In a magnetic disk drive, servo data are usually written on the storage medium once during the manufacture of the drive. The servo patterns typically contain gray-coded track/sector identification (ID) information as well as positioning error information. When read by a magnetic pickup head, these data patterns present themselves as analog waveforms corrupted by electronics and media noise. The servo pulse detection circuit converts the analog pulses in the gray-code ID field of the servo pattern into clearly distinguishable digital pulses so that the information can be further processed using simple logic circuits. A servo error demodulator circuit determines the positioning error of the head relative to the center of the nearest track the head is located on. Conventional servo pulse detectors are typically designed using analog peak detectors similar to the conventional peak detector circuit used for the main data channel in magnetic disk. Integrating the servo channel and the main data channel on a monolithic silicon chip is relatively simple and has been a cost effective solution. However, with the advent of digital maximum likelihood channels which improves the recording density of magnetic disk drives, the main data channel circuitry becomes predominantly digital. Implementing the servo channel using digital circuitry thus become more desirable to ease the integration of the servo and main data channels.
It is desirable to provide a digital circuit technique for servo pulse detection and servo error demodulation which are compatible with the circuit techniques used in a digital read channels.
Several difficulties arise when performing digital pulse peak detection in digital domain. The main problem is that discrete time signal processing introduces a time quantization effect that can be reduced only through using a higher system sampling rate. The present invention uses both system clock edges to perform digital pulse peak detection to mitigate the inaccuracies caused by discrete time signal processing.
The present invention includes an area-based automatic gain control loop. This provides a very desirable feature of generating position error signals that are already normalized and independent of the incoming input frequency spectra when, for example, the head moves across multiple recording zones.
The present invention also includes a differentiating band-pass filter for servo burst filtering, independent of the equalizing filter used for servo pulse detection. The differentiation characteristic of this filter enables the accuracy of position error signal (PES) demodulation to be independent of the offsets in the analog front end circuits of the channel. The bandpass characteristic of the filter removes much of the noise in the PES bursts, resulting in a higher accuracy in PES demodulation in the presence of wide band input noise.
In the following description, we will use the term xe2x80x9cdigital dataxe2x80x9d or xe2x80x9cdigital vectorxe2x80x9d to imply a group of related digital signal bits (e.g., a digital bus, or a group of related digital buses) that represents an analog signal in digital domain. The term xe2x80x9cdigital signalxe2x80x9d refers to a single bit digital line.
The input to the servo channel of the present invention is a first analog signal read back from the servo data field of a storage media. The servo data field contains a synchronization field, followed by a gray-code ID field and then a multiple of position error burst fields.
The servo channel also includes a programmable gain amplifier (PGA) to amplify the first analog signal to a second analog signal. An analog filter filters the second analog signal to provide a third analog signal. An analog to digital converter (ADC) digitizes the third analog signal to provide a first digital data. A digital differentiator receives a first digital data and provides, in response thereto, a second digital data. A digital up-sampler processes the second digital data to provide a plurality of digital data, each of which is an interpolated version of the second digital data at a different sampling delay. The digital up-sampler provides a higher equivalent sampling rate of the system without actually operating any circuits at a higher clock rate. An absolute value function circuit rectifies the interpolated digital data and sums them together to provide a fourth digital data. A digital area-based gain control unit (AGU) compares the signal level of the fourth digital data against a target value and generates a fifth digital data which controls the gain setting of the PGA. The AGU adjusts the gain of the PGA until the signal level of the fourth digital data achieves a certain target value. The signal path starting from the first analog signal to the fifth digital data forms an automatic gain control loop. This loop is active during the synchronization field of the servo loop. The gain of the PGA is frozen after the synchronization field.
A programmable coefficient digital FIR filter equalizes the first digital data to provide a sixth digital data. A digital peak detector processes the sixth digital data to provide a servo pulse signal and an optional pulse polarity signal. The FIR filter and the digital peak detector used to provide a cleanly detected gray-code ID pulses for further servo ID detection by external control logic.
A digital area integrator integrates the fourth digital data to provide a plurality of digital outputs representing the servo position error signal (digital PES). This digital PES data can be read directly by an external servo DSP unit outside of this invention. An optional digital to analog converter (DAC) array converts the digital PES data back to analog PES signals to provide compatibility for back end servo processor systems that expect to receive the demodulated PES signals in analog form.
The digital area gain control unit comprises a first integrator which substantially integrates every half cycle of the servo sync field section of the fourth digital data. This is achieved by making the half cycle period in the servo sync-field substantially equal to an integer multiple of the sampling clock period. The half cycle integrated value is compared against a target level and a difference value is generated and referred to as the gain error data. The gain error data is further accumulated by a second integrator to produce the gain control data for the PGA. The second integrator includes a saturator to prevent overflow or underflow of the gain control data.
The digital peak detector comprises a differentiator, a threshold detector and a zero-crossing detector. The differentiator converts peaks in the incoming data into zero-crossings in its outgoing data. The threshold detector produces a valid-positive-peak data indicator any time the incoming signal is greater than a certain positive threshold, and a valid negative peak indicator when the signal is below a certain negative threshold. The zero-crossing detector produces a negative-servo-pulse output and a positive-servo-pulse output. The negative servo-pulse is asserted when a positive transitioned zero crossing is detected and the valid-negative-pulse output is asserted. The positive servo-pulse is asserted when the negative transitioned zero crossing is detected and the valid-positive-pulse output is asserted. An optional OR gate combines the positive servo-pulse and the negative servo-pulse signals together to provide a composite servo-pulse output. An optional set-reset flip-flop has its set and reset inputs controlled by the negative-servo-pulse and the positive-servo-pulse to provide an output indicating the original polarity of the servo pulse for the composite servo-pulse output. A multiplexer selects either the separated negative/positive servo pulse signals, or the composite and polarity signals as the output of the servo pulse detector.
The digital area integrator for PES demodulation integrates the PES burst field section of the fourth digital data each time the burst gate control signal is asserted. The integration length is the smaller of the burst gate assertion time period and a programmed burst count value. The integrated value is sequentially loaded into a plurality of registers upon every deassertion of the burst gate signal. Under normal operation, the burst gate assertion time period in number of the servo system clock preferably is longer than the programmed burst count value. The user may also program the burst count value so that the total integration time substantially covers an integral multiple of the servo PES burst cycles for improved PES demodulation accuracy.